Semiconductor device

ABSTRACT

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 15/206,319,filed Jul. 11, 2016.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a semiconductor device, and moreparticularly, to a semiconductor device including ferroelectric(hereinafter abbreviated as FE) material and anti-ferroelectric(hereinafter abbreviated as AFE) material.

2. Description of the Prior Art

A semiconductor device means any device which can function by utilizingsemiconductor characteristics, such as an electro-optical device, asemiconductor circuit, and an electronic device. Accordingly,semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment, as example.

Semiconductor devices are typically fabricated by sequentiallydepositing insulating or dielectric layer, conductive layers, andsemiconductor layers over a semiconductor substrate, and patterning thevarious material layers using lithography to form circuit components andelements thereon. Since the semiconductor integrated circuit industryhas experienced rapid growth and improvement, technological advances insemiconductor materials and design have produced increasingly smallerand more complex circuits. Consequently, the number of interconnecteddevices per unit of area has increased as the size of the smallestcomponents that can be reliably created has decreased. However, as thesize of the smallest components has decreased, numerous challenges haverisen. As features become closer, current leakage can become morenoticeable, signals can crossover more easily, and power usage hasbecome a significant concern. Typically, when a gate bias of ametal-oxide-semiconductor field effect transistor (hereinafterabbreviated as MOS FET) device is below the threshold voltage V_(th),the current flow between the source and the drain, which is defined asthe subthreshold current, is supposed to be zero. Or, the subthresholdcurrent was supposed to be very small and thus in early analyticalmodels of the electrical behavior of MOS FET were even assuming a zerooff-state current/subthreshold current. Those skilled in the art shouldhave known there is a linear relationship between the subthresholdcurrent and the gate voltage, which is recognized as subthreshold swing(SS). A small subthreshold swing is highly desired since it improves theratio between the on and off currents, and therefore reduces leakagecurrents. Using a device with a small subthreshold swing therefore hasadvantages such as suppression of power consumption due to reduction inoperation voltage and reduction in off leakage current. However, thesubthreshold swing cannot be less than 60 mV/sec due to the physicallimit of MOSFET device in state-of-the-art. Thus, it is still in need toreduce the subthreshold swing despite the physical limit.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a semiconductor deviceis provided. The semiconductor device includes a substrate, an electrodelayer disposed on the substrate, and a tri-layered gate-control stacksandwiched between the substrate and the electrode layer. Thetri-layered gate-control stack further includes a ferroelectric (FE)layer disposed on the substrate, an anti-ferroelectric (AFE) layersandwiched between the FE layer and the substrate, and a mid-gap metallayer sandwiched between the FE layer and the AFE layer.

According to another aspect of the present invention, a semiconductordevice is provided. The semiconductor device includes a substrate, anelectrode layer disposed on the substrate, and a tri-layeredgate-control stack sandwiched between the substrate and the electrodelayer. The tri-layered gate-control stack further includes an AFE layerdisposed on the substrate, a mid-gap metal layer sandwiched between theAFE layer and the substrate, and a FE layer sandwiched between the AFElayer and the mid-gap metal layer.

According to still another aspect of the present invention, asemiconductor device is provided. The semiconductor device includes asubstrate, an electrode layer disposed on the substrate, and atri-layered gate-control stack sandwiched between the substrate and theelectrode layer. The tri-layered gate-control stack further includes anamorphous dielectric layer, a mid-gap metal layer disposed between theamorphous dielectric layer and the substrate, and a polycrystallinedielectric layer. The mid-gap metal layer directly contacts theamorphous dielectric layer. And the amorphous dielectric layer and thepolycrystalline dielectric layer both include hafnium oxide materials.

According to the semiconductor devices provided by the presentinvention, the tri-layered gate-control stack is provided between theelectrode layer and the substrate, and the tri-layered gate-controlstack includes the FE layer, the AFE layer and the mid-gap metal layer.It is noteworthy that in the tri-layered gate-control stack, the mid-gapmetal layer is always sandwiched between the FE layer and the substratewhile the AFE layer is disposed on or under the dual-layered structureconsisting of the FE layer and the mid-gap metal layer. The FE layer isprovided to enhance electric fields created by the electrode layer andthe mid-gap metal layer is provided to homogenize the enhanced electricfields. Furthermore, the AFE layer is provided to render negativecapacitance effect. The tri-layered gate-control stack is therefore usedto replace conventional high-k gate dielectric layer according to thepresent invention, and the semiconductor device provided by the presentinvention therefore obtains smaller subthreshold swing.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic drawing illustrating a semiconductor deviceprovided by a first preferred embodiment of the present invention, and

FIG. 2 is a schematic drawing illustrating a semiconductor deviceprovided by a second preferred embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 1, which is a schematic drawing illustrating asemiconductor device provided by a first preferred embodiment of thepresent invention. As shown in FIG. 1, a semiconductor device 100 isproved by the preferred embodiment, and the semiconductor device 100includes a substrate 102 such as silicon substrate, silicon-containingsubstrate, or silicon-on-insulator (hereinafter abbreviated as SOI)substrate. A plurality of isolation structures (not shown) is formed inthe substrate 102. The isolation structures can be shallow trenchisolations (STIs), but not limited to this. The isolation structures areused to define a plurality of active regions for accommodating p-typedFET (hereinafter abbreviated as pFET) devices and/or n-typed FET(hereinafter abbreviated as nFET) devices, and to provide electricalisolation. In some preferred embodiments of the present invention, asemiconductor layer such as a fin structure involved in fin field effecttransistor (FinFET) approach can be provided. The fin structure can beformed by patterning a single crystalline silicon layer of a SOIsubstrate or a bulk silicon substrate by photolithographic etchingpattern (PEP) method, multi patterning method, or, preferably, spacerself-aligned double-patterning (SADP), also known as sidewall imagetransfer (SIT) method. And the fin structure can be taken as thesubstrate 102 in the preferred embodiment.

An electrode layer 110 is disposed on the substrate 102. In thepreferred embodiment, metal gate approach is integrated. Accordingly,the electrode layer 110 includes at least a work function metal layer110 a, and the work function metal layer 110 a includes various metalmaterials depending on the conductivity type of the semiconductor device100 to be formed. In some embodiments of the present invention, thesemiconductor device 100 is a p-typed semiconductor device, and the workfunction metal layer 110 a includes any suitable metal material having awork function between about 4.8 eV and about 5.2 eV such as titaniumnitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalumcarbide (TaC), tungsten carbide (WC), or aluminum titanium nitride(TiAlN), but not limited to this. Alternatively, in some embodiments ofthe present invention, the semiconductor device 100 is an n-typedsemiconductor device, and the work function metal layer 110 a includesany suitable metal material having a work function between about 3.9 eVand about 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide(ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), or hafniumaluminide (HfAl), but not limited to this. Additionally, the workfunction metal layer 110 a can be a single-layered structure or amulti-layered structure. The electrode layer 110 further includes agap-filling metal layer 110 b, and the gap-filling metal layer 110 b canbe a single metal layer or a multiple metal layer including superior gapfiling ability, such as Al, Ti, Ta, W, Nb, Mo, Cu, TiN, TiC, TaN, Ti/W,or Ti/TiN, but not limited to this. Furthermore, it is well-known tothose skilled in the art that a bottom barrier layer, an etch stoplayer, and/or a top barrier layer can be included in the electrode layer110 if required. As shown in FIG. 1, a bottom barrier layer 112 issandwiched between the electrode layer 110 and the substrate 100, and anetch stop layer 114 is sandwiched between the electrode layer 110 andthe bottom barrier layer 112. Additionally, a top barrier layer (notshown) can be sandwiched between the work function metal layer 110 a andthe gap-filling metal layer 110 b. The etch stop layer 114 preferablyincludes material including etching rate different from the bottombarrier layer 112. For example but not limited to, the bottom barrierlayer 112 can be a TiN layer and the etch stop layer 114 can be a TaNlayer.

Please still refer to FIG. 1. The semiconductor device 100 provided bythe preferred embodiment further includes a tri-layered gate-controlstack 120 sandwiched between the substrate 102 and the electrode layer110. The tri-layered gate-control stack 120 includes a FE layer 122disposed on the substrate 102, an AFE layer 126 sandwiched between theFE layer 122 and the substrate 102, and a mid-gap metal layer 124sandwiched between the FE layer 122 and the AFE layer 126. In someembodiments of the present invention, the FE layer 122 includes amaterial selected from the group consisting of lead zirconate titanate(bZrTiO₃, PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O₃, PLZT),strontiumbismuthtantalate (SrBiTa₂O₉, SBT), bismuth lanthanum titanate((BiLa)₄Ti₃O₁₂, BLT), and barium strontium titanate (BaSrTiO₃, BST). TheAFE layer 126 includes a material selected from the group consisting oflead indium niobate (Pb(InNb)O₃), niobium-sodium oxide (NbNaO₃), leadzirconate (ZrPbO₃), lead lanthanum zirconate titanate (TiZrLaPbO₃), leadzirconate titanate (TiZrPbO₃), ammonium dihydrogen phosphate (NH₄H₂PO₄,ADP), and ammonium dihydrogen arsenate (NH₄H₂AsO₄, ADA). It isnoteworthy that the FE layer 122 and the AFE layer 126 can include thesame elementary material but with different crystalline morphologiesand/or composition ratio. For example, both of the FE layer 122 and theAFE layer 126 can include hafnium oxide material such as HfZrO_(x), butthe FE layer 122 includes amorphous HfZrO_(x) while the AFE layer 126includes polycrystalline HfZrO_(x). It is noteworthy that hafnium oxidematerial can still include other elementary material such as Zr inaccordance with the present invention. In other words, in someembodiments of the present invention, the FE layer 122 is taken as anamorphous or a fractionally crystalized dielectric layer and the AFElayer 126 is taken as a polycrystalline dielectric layer. The mid-gapmetal layer 124 includes metal having a work function between valenceband and conduction band. The mid-gap metal layer 124 includes metalnitride such as, for example but not limited to, TiN, TaN, titaniumsilicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or molybdenumnitride (MoN). In other embodiments of the present invention, themid-gap metal layer 124 can include nickel silicide (NiSi), tungstensilicide (WSi), cobalt silicide (CoSi₂), or titanium tungsten (TiW), butnot limited to this.

It is noteworthy that since an antiferromagnetic state will transfer toa paramagnetic state at a temperature over the Neel temperature, high-klast approach is adopted in the preferred embodiments of the presentinvention in order to avoid the above mentioned issue. It is well-knownto those skilled in the art that in the high-k last approach, a dummygate or a replacement gate (not shown) is formed on the substrate 102and followed by forming elements of a FET device such as light dopeddrains (LDDs) 106, a spacer 104, and a source/drain 108. The dummy gateincludes a dielectric layer (not shown), a conductive layer such as apolysilicon layer (not shown), and a patterned hard mask (not shown).The spacer 104 can be a single-layered structure or a multi-layeredstructure, but not limited to this. Furthermore, selective strain scheme(SSS) can be used in the preferred embodiments of the present invention.For example, a selective epitaxial growth (SEG) method can be used toform the source/drain. When the semiconductor device 100 is the p-typedtransistor, epitaxial silicon layers of SiGe are used to form thesource/drain. When the semiconductor device 100 is the n-typedtransistor, epitaxial silicon layers of SiC or SiP are used to form thesource/drain. Additionally, salicides (not shown) can be formed on thesource/drain 108. After forming the semiconductor device 100, an etchliner such as a contact etch stop layer (hereinafter abbreviated asCESL) (not shown) is selectively formed on the substrate 100, and aninterlayer dielectric (hereinafter abbreviated as ILD) layer 130 issubsequently formed. Next, a planarization process such as chemicalmechanical polishing (CMP) process is performed to planarize the ILDlayer 130 and the CESL. The patterned hard mask is then removed toexpose the conductive layer of the dummy gate and followed by removingthe conductive layer and the dielectric layer of the dummy gate.Consequently, a gate trench (not shown) is formed on the substrate 102.In some preferred embodiments of the present invention, an oxide liner128 can be formed in the gate trench and followed by forming thetri-layered gate-control stack 120 in the gate trench. And after formingthe tri-layered gate-control stack 120, the abovementioned metal layersare formed. Accordingly, the tri-layered gate-control stack 120 includesa U shape in the preferred embodiments. The oxide liner 128 serves as aninterfacial layer (IL), and the interfacial layer provides a superiorinterface between the substrate 102 and the tri-layered gate-controlstack 120. Additionally, the bottom barrier layer 112 and the etch stoplayer 114 are sandwiched between the tri-layered gate-control stack 120and the electrode layer 110 as shown in FIG. 1. It should be easilyunderstood to those skilled in the art that in still other preferredembodiments of the present invention, high-k first approach can beadopted and thus the tri-layered gate-control stack 120 includes a flapshape in those preferred embodiments.

According to the semiconductor device 100 provided by the preferredembodiment, the tri-layered gate-control stack 120 sandwiched betweenthe electrode layer 110 and the substrate 102 is provided. The FE layer122 (or, the material layer including the ferroelectric characteristicdue to its amorphous or fractionally crystalized morphology, such as theamorphous or fractionally crystalized dielectric layer) of thetri-layered gate-control stack 120 is used to enhance the electricfields created by the electrode layer 110. However, it is found theelectric fields enhanced by the FE layer 122 are inhomogeneous.Therefore, the mid-gap metal layer 124 sandwiched between the FE layer122 and the substrate 102 is provided. The mid-gap metal layer 124directly contacts the FE layer (the amorphous or fractionallycrystalized dielectric layer) and homogenizes the electric fieldsenhanced by the FE layer 122. Furthermore, the AFE layer 126 (thematerial layer including anti-ferroelectric characteristic due to itspolycrystalline morphology, such as the polycrystalline dielectriclayer) is provided to render negative capacitance effect. Consequently,the subthreshold swing is reduced. Compared with the device includingthe convention high-k gate dielectric layer, the subthreshold swing ofthe semiconductor device 100 provided by the present invention issignificantly reduced from 60 mV/dec to 10 mV/dec, which is beyond thephysical limit. And thus both leakage current and power consumption arereduced.

Please refer to FIG. 2, which is a schematic drawing illustrating asemiconductor device provided by a second preferred embodiment of thepresent invention. It should be noted that elements the same in thefirst and second preferred embodiments can be formed by the same methodwith the same material, thus those details are omitted in the interestof brevity. As shown in FIG. 2, a semiconductor device 200 is proved bythe preferred embodiment, and the semiconductor device 200 includes asubstrate 202. A plurality of isolation structures (not shown) is formedin the substrate 202. The isolation structures are used to define aplurality of active regions for accommodating pFET devices and/or nFETdevices, and to provide electrical isolation. Furthermore, asemiconductor layer such as a fin structure involved in FinFET approachcan be provided and taken as the substrate 202 in some preferredembodiments of the present invention.

An electrode layer 210 is disposed on the substrate 202. In thepreferred embodiment, metal gate approach is integrated. Accordingly,the electrode layer 210 includes at least a work function metal layer210 a, and the work function metal layer 210 a includes various metalmaterials depending on the conductivity type of the semiconductor device200 to be formed: In some embodiments of the present invention, thesemiconductor device 200 is a p-typed semiconductor device, and the workfunction metal layer 210 a includes any suitable metal material having awork function between about 4.8 eV and about 5.2 eV. Alternatively, insome embodiments of the present invention, the semiconductor device 200is an n-typed semiconductor device, and the work function metal layer210 a includes any suitable metal material having a work functionbetween about 3.9 eV and about 4.3 eV. Additionally, the work functionmetal layer 210 a can be a single-layered structure or a multi-layeredstructure. The electrode layer 210 further includes a gap-filling metallayer 210 b, and the gap-filling metal layer 210 b can be a single metallayer or a multiple metal layer including superior gap filing ability.Furthermore, it should be easily understood to those skilled in the artthat a bottom barrier layer, an etch stop layer, and/or a top barrierlayer can be included in the electrode layer 210 if required. As shownin FIG. 2, a bottom barrier layer 212 is sandwiched between theelectrode layer 210 and the substrate 200 while an etch stop layer 214is sandwiched between the electrode layer 210 and the bottom barrierlayer 212. Additionally, a top barrier layer (not shown) can besandwiched between the work function metal layer 210 a and thegap-filling metal layer 210 b. And the etch stop layer 214 preferablyincludes material including etching rate different from the bottombarrier layer 212.

Please still refer to FIG. 2. The semiconductor device 200 provided bythe preferred embodiment further includes a tri-layered gate-controlstack 220 sandwiched between the substrate 202 and the electrode layer210. The tri-layered gate-control stack 220 includes an AFE layer 226disposed on the substrate 202, a mid-gap metal layer 224 sandwichedbetween the AFE layer 226 and the substrate 202, and a FE layer 222sandwiched between the AFE layer 226 and the mid-gap metal layer 224. Asmentioned above, the FE layer 222 and the AFE layer 226 can includedifferent materials, or the same elementary material but with differentcrystalline morphologies and/or composition ratio. In other words, theFE layer 222 can be taken an amorphous or a fractionally crystalizeddielectric layer while the AFE layer 226 can be taken as apolycrystalline dielectric layer.

As mentioned afore, since an antiferromagnetic state will transfer to aparamagnetic state at a temperature over the Neel temperature, high-klast approach is adopted in preferred embodiments of the presentinvention in order to avoid the above mentioned issue. It is well-knownto those skilled in the art that in the high-k last approach, a dummygate or a replacement gate (not shown) is formed on the substrate 202and followed by forming elements of a FET device such as LDDs 206, aspacer 204, and a source/drain 208. And after forming a CESL (not shown)and an ILD layer 230, the dummy gate is removed to form a gate trench(not shown) on the substrate 202. In some preferred embodiments of thepresent invention, an oxide liner 228 can be formed in the gate trenchand followed by forming the tri-layered gate-control stack 220 in thegate trench. And after forming the tri-layered gate-control stack 220,the abovementioned metal layers are formed. Accordingly, the tri-layeredgate-control stack 220 includes a U shape in the preferred embodiments.The oxide liner 228 serves as an interfacial layer, and the interfaciallayer provides a superior interface between the substrate 202 and thetri-layered gate-control stack 220. Additionally, the bottom barrierlayer 212 and the etch stop layer 214 are sandwiched between thetri-layered gate-control stack 220 and the electrode layer 210 as shownin FIG. 2. It should be easily understood to those skilled in the artthat in still other preferred embodiments of the present invention,high-k first approach can be adopted and thus the tri-layeredgate-control stack 220 includes a flap shape in those preferredembodiments.

According to the semiconductor device 200 provided by the preferredembodiment, the tri-layered gate-control stack 220 sandwiched betweenthe electrode layer 210 and the substrate 202 is provided. The FE layer222 (or the amorphous or fractionally crystalized dielectric layer) ofthe tri-layered gate-control stack 220 is used to enhance the electricfields created by the electrode layer 210. However, it is found theelectric fields enhanced by the FE layer 222 are inhomogeneous.Therefore, the mid-gap metal layer 224 sandwiched between the FE layer222 and the substrate 202 is provided. The mid-gap metal layer 224directly contacts the FE layer (the amorphous or fractionallycrystalized dielectric layer) and homogenizes the electric fieldsenhanced by the FE layer 222. Furthermore, the AFE layer 226 (thepolycrystalline dielectric layer) is provided to render negativecapacitance effect. Consequently, the subthreshold swing is reduced.Compared with the device including the convention high-k gate dielectriclayer, the subthreshold swing of the semiconductor device 200 providedby the present invention is significantly reduced to be lower than 60mV/dec, which is still beyond the physical limit. And thus both leakagecurrent and power consumption are reduced.

According to the semiconductor devices provided by the presentinvention, the tri-layered gate-control stack is provided between theelectrode layer and the substrate, and the tri-layered gate-controlstack includes the FE layer (or the amorphous or fractionallycrystalized dielectric layer in some conditions), the AFE layer (or thepolycrystalline dielectric layer in some conditions), and the mid-gapmetal layer. It is noteworthy that in the tri-layered gate-controlstack, the mid-gap metal layer is always sandwiched between the FE layerand the substrate while the AFE layer is disposed on or under thedual-layered structure consisting of the FE layer and the mid-gap metallayer. Preferably, the mid-gap metal layer directly contacts the FElayer. The FE layer is provided to enhance electric fields of theelectrode layer and the mid-gap metal layer is provided to homogenizethe enhanced electric fields. Furthermore, the AFE layer is provided torender negative capacitance effect. The tri-layered gate-control stackis therefore used to replace conventional high-k gate dielectric layeraccording to the present invention, and the semiconductor deviceprovided by the present invention obtains smaller subthreshold swing,and thus both leakage current and power consumption are reduced.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A semiconductor device comprising: a substrate; an electrode layer disposed on the substrate; and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising: an anti-ferroelectric (AFE) layer disposed on the substrate; a mid-gap metal layer sandwiched between the AFE layer and the substrate; and a ferroelectric layer sandwiched between the AFE layer and the mid-gap metal layer.
 2. The semiconductor device according to claim 1, wherein the electrode layer comprises at least a work function metal layer.
 3. The semiconductor device according to claim 1 further comprising an oxide liner layer sandwiched between the mid-gap metal layer of the tri-layered gate-control stack and the substrate.
 4. The semiconductor device according to claim 1, wherein the ferroelectric layer comprises a material selected from the group consisting of lead zirconate titanate (bZrTiO₃, PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O₃, PLZT), strontium bismuth tantalite (SrBiTa₂O₉, SBT), bismuth lanthanum titanate ((BiLa)₄Ti₃O₁₂,BLT), and barium strontium titanate (BaSrTiO3, BST).
 5. The semiconductor device according to claim 1, wherein the mid-gap metal layer comprises metal nitride.
 6. The semiconductor device according to claim 1, wherein the AFE layer comprises a material selected from the group consisting of lead indium niobate (Pb(InNb)O₃), niobium-sodium oxide (NbNaO₃), lead zirconate (ZrPbO₃), lead lanthanum zirconate titanate (TiZrLaPbO₃), lead zirconate titanate (TiZrPbO₃), ammonium dihydrogen phosphate (NH₄H₂PO₄, ADP), and ammonium dihydrogen arsenate (NH₄H₂AsO₄, ADA).
 7. The semiconductor device according to claim 1, further comprising a bottom barrier layer and an etch stop layer sandwiched between the tri-layered gate-control stack and the electrode layer.
 8. The semiconductor device according to claim 1, wherein the tri-layered gate-control stack comprises a U shape. 